Digital-analogue conversion based on converting a delta-sigma digital representation of a signal into an analogue waveform is now a commonplace technique. In a simple delta-sigma digital-to-analogue converter a string of pulses is generated, with a pulse density dependent upon the digital value to be converted, and low-pass filtered. The technique is prevalent in many high-volume application areas, for example digital audio, where several channels of high quality relatively low frequency (audio frequency) signals are required. High quality in this context typically implies −100 dB THD (Total Harmonic Distortion) and 100 dB SNR (Signal to Noise Ratio). However, in such high-volume markets manufacturing cost is also very important.
In general, a digital-to-analogue converter requires positive and negative reference voltages to define the amplitude of the output signal. A digital-to-analogue converter draws some current from these reference voltage ports, and this current will generally be signal dependent.
These reference voltages are typically generated from a source of low but non-zero output impedance, for example by a power supply or buffer with a decoupling capacitor. The source will have a finite ESR (Equivalent Series Resistance), and there will be additional resistance between the source, the decoupling and the device due to the effects of resistive PCB tracking, package lead resistance, and bond wire resistance.
The result is that any signal-dependent current drawn by the DAC from the references causes a signal-dependent voltage ripple to appear on the reference voltages actually applied to the DAC. Since the DAC output signal is proportional to the reference voltage, this multiplies the ideal digital-to-analogue converter output by this ripple. The consequent modulation of the output signal is apparent as signal distortion, for example, generating harmonic distortion components with a sine wave signal.
Furthermore in a stereo or multi-channel system it is often uneconomic to supply a digital-to-analogue converter for each channel with a separate voltage reference supply, or even separate decoupling, PCB traces, or integrated circuit pins. In these situations the reference ripple caused by one channel's DAC can appear on the reference voltage for other DACs, modulating the outputs of these other DACs as well as its own output.
The invention described herein is directed to digital-to-analogue converter circuits intended to reduce or eliminate signal dependent reference currents. A digital-to-analogue converter design for which the reference currents are substantially independent of output signal should be capable of lower distortion for a given source impedance. Alternatively, for a given acceptable level of performance, the digital-to-analogue converter should be more tolerant of source impedance, so allowing a design engineer to reduce costs by specifying fewer or cheaper, lower quality external components.
Many delta-sigma digital-to-analogue converters use switched-capacitor techniques. FIG. 1a shows an example of a simple switched-capacitor DAC 100 suitable for use in a delta-sigma DAC system.
An operational amplifier 102 has a non-inverting input connected to a constant voltage Vmid 118, typically ground. Operational amplifier 102 has an output 120 providing an output voltage Vout and a feedback capacitor Cf 104 is connected between the output and an inverting input of the operational amplifier. A second capacitor C2 106 is switchably connected across feedback capacitor 104 by means of switches 108 and 110. Switch 108 allows one plate of capacitor 106 to be connected either to Cf 104 or to a positive reference voltage VP 112 or a negative reference voltage VN 114. Switch 110 allows the other plate of capacitor 106 to be connected either to feedback capacitor 104 or to a second constant voltage, Vmid2 116.
In operation switches 108 and 110 are controlled respective by two-phase, preferably non-overlapping clocks supplied by a clock generator (not shown in FIG. 1). As shown in FIG. 1b, each of these clock signals comprises a charge phase Phi1 during which switch 110 is connected to Vmid2 and switch 108 is connected to either VP or VN, and capacitor C2 106 is charged and a dump phase Phi2 during which switch 110 is connected to Cf and switch 108 is connected to Cf, and the charge on capacitor C2 106 is shared with or dumped to the feedback capacitor Cf 104. This clocking scheme can conveniently be represented by the table of FIG. 1c, reproduced below as Table 1a.
TABLE 1aSwitch positions versus clock phase for the circuit of FIG. 1aConnected to:SwitchDuring Phi1 (Charge)During Phi2 (Dump)110Vmid2Cf108VP/VNCf
Henceforth clocking schemes for subsequent circuits will likewise be represented by tables along the lines of table 1a, these representing corresponding, preferably non-overlapping switch control clock signals.
FIG. 1d shows an example of a clock generator circuit 150 for the circuit of FIG. 1a. The input data signal is DIN. An external clock CKIN generates non-overlapping clocks CK1 and CK2. CK1 is ON in clock phase Phi1, CK2 is ON in clock phase Phi2. CK2 can thus be used to drive the poles of switches 108 and 110 connecting to Cf during Phi2, and CK1 is suitable to drive the pole of switch 110 connecting to Vmid2 during Phi1. To drive the remaining poles of switch 108 during Phi1 to VP when DIN is high and VN when DIN is low, clocks CK1A and CK1B are generated by the AND gates 152a and 152b. The operation of these clocks is summarised in the expanded version of Table 1a, in Table 1b below, where the clocks in the right-hand column correspond to the connections shown in the centre two columns.
TABLE 1bConnected to:During Phi1During Phi2Switch(Charge)(Dump)By Clock:110Vmid2CK1CfCK2108VP/CK1AVNCK1BCfCK2
FIG. 1e shows a timing diagram the circuit of FIG. 1d, in particular CKIN 160, DIN 162 (11001 . . . ), CK1 164, CK2 166, CK1A 168a, & CK1B 168b; note the underlap of clocks CK1, CK2, and CK1A, CK1B alternating according to DIN.
In more detail, during the charging phase Phi1 capacitor C2 is charged, with Vmid2 (generally the same voltage as Vmid) applied to one terminal via switch 110 and VP or VN applied to the other terminal via switch 108. Typically values of VP 112 and VN 114 are +3V and −3V respectively, with respect to Vmid 118. The choice of VP or VN for any particular cycle is defined by a digital delta-sigma signal applied to switch 108 during this charging phase Phil1. During the dump phase, Phi2, C2 is disconnected from VP, VN and Vmid2 and connected in parallel with the op amp feedback capacitor Cf 104 via switches 110 and 108.
Typically C2 106 is much smaller than the op amp feedback capacitor Cf 104. The left-hand side of C2 is switched between a voltage equal to Vmid 118 (since the inverting terminal of op amp 102 is a virtual earth, that is it is at substantially the same voltage as the non-inverting terminal) and Vmid2. Assume for simplicity that as usual Vmid2=Vmid. Then if VP rather than VN is applied to the other end of C2 during Phi1 for many consecutive clock cycles, the output Vout 120 will converge to equal VP 112, to achieve a steady state in which both the left-hand side and the right-hand side of C2 106 are switched between equal voltages each cycle. Similarly if VN 114 is applied each cycle, Vout will converge to VN 114. If VP and VN are each applied half the time, the output 120 will be the average of VP and VN. In general for a VP:VN duty cycle of m:(1−m), the steady-state output will be given by:Vout=m*VP+(1−m)*VN  (Equation 1)
For example, if m=0.9, Vout=0.9VP+0.1VN. In this context “duty cycle” should be understood as the fraction, proportion or ratio of the number of connections to VP to the number of connections to VN, for example measured in clock cycles.
In general m will vary with time, corresponding to the varying value of the input audio signal, but the clock frequency is generally much higher than a typical audio frequency, so it is a good approximation to discuss operation in terms of an m value constant over many cycles.
The duty cycle m is controlled by a digital delta-sigma signal to alternately connect C2 106 to VP and VN to provide the required output voltage 120. This output voltage 120 will vary from VP to VN according to the duty cycle applied. Thus, in effect, the DAC circuit may be considered as having a gain from the voltages (112 and 114) applied to the switched capacitor to the output 102 defined by (Vout,max−Vout,min)/(VP−VN) of substantially unity.
The skilled person will recognise that the gain of circuit 100 may be adjusted, for example, by connecting a voltage divider to output 120 and taking the voltage for capacitor Cf 104 from a tap point on this divider, for example to provide a gain of 2. However typically the circuit will have a relatively low gain, for example less than 10 and more typically less than 3. This also applies to the DAC circuits which are described later.
An earlier patent of one of the inventors, U.S. Pat. No. 6,573,850, recognised that the above-described prior art DAC circuit suffers from a problem associated with signal-dependent loading of reference voltage sources for voltages VP 112 and VN 114. The way in which this problem arises and the solution provided by U.S. Pat. No. 6,573,850 is discussed further below. Other background prior art (also referenced in U.S. Pat. No. 6,573,850) can be found in U.S. Pat. No. 5,790,064 (a switched capacitor integrator which does not operate on the principle of charge sharing but instead dumps charge into an input of an operational amplifier which in turn drives an integration capacitor), U.S. Pat. No. 5,703,589 and FR 2,666,708 (other switched capacitor integrators), all for analogue-to-digital converter circuits and not intended or suitable for use as high quality digital-to-analogue converters; U.S. Pat. No. 4,896,156, U.S. Pat. No. 4,994,805, EP 0 450 951 (and U.S. Pat. No. 5,148,167), U.S. Pat. No. 6,081,218, U.S. Pat. No. 6,337,647, EP 1 130 784, and “A 120 dB Multi-bit SC Audio DAC with Second Order Noise Shaping”, J Rhode, Xue-Mei Gong et al., pages 344–5 in IEEE Solid State Circuit Conference Procs. (ISSCC) 2000.
The manner in which signal-dependent reference source loading arises in the DAC circuit of FIG. 1 can be seen by considering the charge taken from VP and VN averaged over many cycles. For the above m:(1−m) duty cycle, and assuming for simplicity that C2<<Cf, so that cycle-by-cycle ripple on Vout is small, for VP this is given by:                m*(VP−Vout)*C2        =m*(VP−(m*VP+(1−m)*VN))*C2        =m*(1−m)*(VP−VN)*C2This has a parabolic dependence on m, with zeros at m=0 and m=1, and a maximum of 0.25*(VP−VN)*C2 at m=0.5. Loading of VN shows a similar dependence.        
FIG. 2 shows a digital-to-analogue converter 200 with a differential voltage output 120a, b, based upon the circuit of FIG. 1. As can be seen from inspection of FIG. 2, the differential DAC 200 comprises two similar but mirrored circuits 100a, 100b, each corresponding to DAC 100. The positive differential signal processing circuit portion 100a generates a positive output Vout+ 120a and the negative differential signal processing portion 100b generates a negative voltage output Vout− 120b. Likewise the positive circuit portion 100a is coupled to first reference voltage supplies VP+ 112a and VN+ 114a and the negative circuit portion 100b is coupled to second reference voltage supplies VP− 112b and VN− 114b. 
Preferably VP+ 112a and VP− 112b are supplied from a common positive reference voltage source and VN+ 114a and VN− 114b are supplied from a common negative reference voltage source. Thus preferably VP+ and VP− are at the same voltage and VN+ and VN− are at the same voltage. As can be seen C2+ 106a is switched to references VP+ 112a and VN+ 114a and C2− 106b is switched to references VP− 112b and VN− 114b. Voltages Vmid2+ 116a and Vmid2− 116b preferably have the same value, preferably the value of Vmid 118, typically ground. Preferably feedback capacitors 104a, b and switched capacitors 106a, b have the same value and op amps 102a and 102b are matched. Op amps 102a, b may comprise a single differential-input, differential-output op amp. These same comments also apply to the later described differential DAC circuits.
A clocking scheme for the DAC of FIG. 2 is shown in Table 2 below:
TABLE 2Switch positions versus clock phase for thedifferential circuit of FIG. 2Connected to:SwitchDuring Phi1 (Charge)During Phi2 (Dump)110aVmid2+Cf+110bVmid2−Cf−108aVP+/VN+Cf+108bVN−/VP−Cf−
Continuing to refer to FIG. 2, in operation, whenever VP+ is chosen to charge C2+, then VN− is selected to charge C2−. Thus by symmetry, from equation (1) above, one can writeVout−=m*VN−+(1−m)*VP−  (Equation 2)
When, for example, m=0.9, Vout−=0.9 VN−+0.1 VP−; when m=0.5, Vout+=Vout−=(VP+VN)/2. As m varies Vout+ and Vout− will swing in equal amplitude but opposite polarities about this common-mode (m=0.5) voltage.
The average charge taken from VP+ will be as above:                m*(VP+−Vout+)*C2+        =m*(VP+−(m*VP+(1−m)*VN))*C2        =m*(1−m)*(VP+−VN+)*C2+        
The average charge taken from VP− will be:                (1−m)*(VP−−Vout−)*C2−        =(1−m)*(VP−m*VN−−(1−m)*VP−)*C2−        =(1−M)*m(VP−−VN−)*C2−        
Thus the average total charge taken from VP (that is VP+ and VP−) is 2*m*(1−m)*(VP−VN)*C2 (where VP+=VP−=VP and C2+=C2−=C2). This is just double the charge of the single-sided implementation, as might be surmised by the symmetries of the circuit. Again the function is parabolic, with a minimum of zero (for m=0 or 1) and a maximum of 0.5*(VP−VN)*C2.
To take an example, consider a case where VP=+3V, VN=−3V, and C2=10 pF. Assuming the circuit is clocked at 10 MHz, this will give rise to a current varying from zero to 0.5*(+3V−(−3V))*10 pF*01 MHz=300 μA drawn from VP and VN depending on the low-frequency level of the output signal Vout. If the equivalent source impedance of the sources of VP and VN are 1 ohm each, this will give a modulation of (VP−VN) of 0.6 m Vpk−pk., that is 0.1% of (VP−VN). This will modulate the output signal by a similar amount (as with a multiplying DAC) and is a gross effect in a system aimed at typically −100 dB (0.001%) THD.
FIG. 3 shows a multibit differential switched capacitor DAC 300, a common extension to the circuit of FIG. 2. In this extension multiple independently switched capacitors are used in place of the capacitor C2+ (and C2−). Although FIG. 3 shows just two additional capacitors for each circuit 106aa,bb (for simplicity) and four corresponding additional switches 108aa,bb, 110aa,bb, in practice a plurality of additional capacitors and switches may be provided for each differential signal processing circuit portion. A clocking scheme for this circuit is given in Table 3 below.
TABLE 3Switch positions versus clock phase for themulti-bit differential circuit of FIG. 3Connected to:SwitchDuring Phi1 (Charge)During Phi2 (Dump)110aVmid2+Cf+110bVmid2−Cf−108aVP+/VN+Cf+108bVN−/VP−Cf−110aaVmid2+Cf+110baVmid2−Cf−108aaVP+/VN+Cf+108baVN−/VP−Cf−. . .
In effect, the switched capacitors C2 of FIG. 3 may be replaced by an array of capacitors. The capacitors in such arrays may or may not be binary weighted. In one arrangement the LSB capacitors are binary weighted, but the MSB capacitors are equally weighted, and used in a random manner to decrease the effects of mismatch. Suitable methods for deriving the necessary multi-bit delta-sigma digital control waveforms, to define the cycle-by-cycle connections to VP or VN of each capacitor in these arrays, are well known to those skilled in the art and described, for example, in “Delta-sigma data converters—theory design and simulation” edited by Steven R Norsworthy, Richard Schreier, Gabor C Temes, IEEE Press, New York 1997, ISBN 0-7803-1045-4, hereby incorporated by reference. Analysis of this circuit gives a similar variation in reference loading with signal.
There is therefore a need for charge-sharing, switched capacitor DAC circuits which exhibit reduced signal-dependent loading of reference sources.
The circuit of U.S. Pat. No. 6,573,850 achieves this by briefly connecting the switched capacitor to a substantially signal-independent reference voltage prior to connection of this capacitor to one of the reference voltages. Connecting the switched capacitor to a substantially signal-independent reference before connecting it to one of the references allows signal-dependent charges to flow onto or off the switched capacitor before the capacitor is recharged. In other words the charge on the switched capacitor may be brought to a substantially signal-independent or predetermined state of charge prior to its connection to one of the references, so that there is little or no signal-dependent loading of these references. However the circuits of U.S. Pat. No. 6,573,850 require an additional clock phase to be generated and distributed, and generally also require the generation of a suitable signal-independent reference voltage.
Two further issues arise with high performance switched-capacitor audio DACs, firstly problems of flicker noise (sometimes called 1/f noise) in the MOS devices typically used to implement the op amps, and secondly problems with crosstalk between amplifiers due to combinations of common supply impedances, poor audio-frequency supply decoupling, and finite op amp power-supply rejection.
Flicker noise power is approximately inversely proportional to the area of the devices used, so to gain 6 dB in reduced flicker noise requires input devices of four times the area. For SNR of 100 dB or greater (120 dB is becoming a target for high-performance systems), it rapidly becomes impractical to achieve a flicker noise corner frequency below say 1 kHz, and even then with a significant impact on chip area and hence cost.
The load regulation bandwidth of active power supplies is often inadequate to prevent millivolts of ripple at higher audio frequencies, especially as these supplies may also be supplying high-power outputs to drive speakers or headphones. Often several channels of DAC (e.g. six) are implemented on the same silicon chip but without the expense of extra supply pins it is difficult to distribute the supplies to all amplifiers (including power output stages) without several ohms of common supply impedance. The resulting modulation of the local supply voltage of each channel in conjunction with the finite supply rejection of the op amps, itself diminishing with high audio frequency, can be a significant source of crosstalk between channels relative to a typical target of 100 dB.
Both the op amp flicker noise and op amp supply rejection (or rather lack of it) can be modelled as a modulation of the input offset voltage of the op amps in question. One known technique for mitigating these effects is the “chopper” technique. FIG. 4 shows this applied to a simple DAC circuit 400. Table 4, below, shows a clocking scheme for the DAC of FIG. 4.
TABLE 4Switch positions versus clock phase for thechopped differential DAC circuit of FIG. 4Connected to:During Phi1During Phi2During Phi3During Phi4Switch(Charge)(Dump)(Charge)(Dump)110aVmid2+Cf+Vmid2+Cf+110bVmid2−Cf−Vmid2−Cf−108aVP+/VN+Cf+VP+/VN+Cf+108bVN−/VP−Cf−VN−/VP−Cf−401aCf+Cf+Cf−Cf−401bCf−Cf−Cf+Cf+402aCf+Cf+Cf−Cf−402bCf−Cf−Cf+Cf+
In the differential circuit of FIG. 4 the difference in offsets between the two op amps is modelled as an effective offset Voff to the first op amp 102a. In one clock cycle, op amp 102a is connected to one feedback capacitor, and its effective offset Voff affects the output of the respective output, Vout+ by Voff. In the next clock cycle, op amp 102a is connected to the other symmetric half of the capacitor network, and has the same effect on the negative output Vout−. The low-frequency offset of the op amp thus appears on the outputs as a common-mode average signal of Voff/2, together with a differential output as a modulation of +/−Voff/2 at fs/2 where fs is the sample rate of the input signal (ie. the charge-dump cycle frequency), but there is no corresponding low-frequency differential signal. In embodiments the high frequency components are filtered out by a subsequent post-filter preferably employed in any case to attenuate the ultrasonic high-frequency delta-sigma quantisation noise components.
The differential DAC circuits of U.S. Pat. No. 6,573,850 are intended to provide a substantially constant load on a clock cycle-by-cycle basis, for example to give a constant charge load on VP each clock cycle. We will now describe alternative schemes, based on a different but related principle, providing a substantially constant charge load only when averaged over multiple clock cycles. This is nonetheless useful, since the clock frequency is normally much greater than the signal frequency and thus any artefacts at half the clock frequency can be easily post-filtered. In any case some post-filtering is generally required because of spikes of current on VP and VN at the clock frequency.